As opposed to planar complementary metal oxide semiconductor (CMOS) devices, vertical field effect transistors (VFETs) are oriented with a vertical fin channel disposed on a bottom source/drain and a top source/drain disposed on the fin channel. VFETs are being explored as a viable device option for continued CMOS scaling beyond the 7 nanometer (nm) technology node.
A typical VFET device includes a vertical fin that extends upward from the substrate. The fin forms the channel region of the transistor. A source region and a drain region are situated in electrical contact with the top and bottom ends of the channel region, while the gate is disposed on one or more of the fin sidewalls. One challenge for fabricating VFET is to achieve a sharp junction and low extension resistance at the interface between the source/drain and the channel. One approach to form the bottom source/drain in a VFET process flow is via ion implantation. However, implantation of dopant species tends to damage the vertical fin channel.
Another approach to forming a VFET bottom source/drain is by thermally-driven diffusion. While thermally-driven diffusion of dopant species can avoid damaging the fin channel, the diffusion process can be difficult to control to achieve the desired sharp, well-defined junction.
Therefore, techniques are needed for forming a VFET device with sharp, well-defined junctions.